Talha's Physics Academy
Universal Logic Gates: NAND and NOR Gates
Video Lecture: NAND and NOR Gates
Watch the complete video lecture explaining the definitions, boolean expressions, and truth tables of NAND and NOR gates:
4. NAND Gate
“The NAND gate is a logic gate that produces a low output ($0$) only when all the inputs are high ($1$). It is formed by the combination of an AND gate followed by a NOT gate (NOT-AND).”
Boolean Expressions
- Two Inputs: $X = \overline{A \cdot B}$
- Three Inputs: $X = \overline{A \cdot B \cdot C}$
- Four Inputs: $X = \overline{A \cdot B \cdot C \cdot D}$
Fig: Logic symbols for NAND gates.
Truth Tables
i) Two Inputs
| Input | Output | |
|---|---|---|
| A | B | X |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
ii) Three Inputs
| Input | Output | ||
|---|---|---|---|
| A | B | C | X |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
iii) Four Inputs
| Input | Output | |||
|---|---|---|---|---|
| A | B | C | D | X |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
5. NOR Gate
“The NOR gate is a logic gate that produces a high output ($1$) only when all of its inputs are low ($0$). It is formed by the combination of an OR gate followed by a NOT gate (NOT-OR).”
Boolean Expressions
- Two Inputs: $X = \overline{A + B}$
- Three Inputs: $X = \overline{A + B + C}$
- Four Inputs: $X = \overline{A + B + C + D}$
Fig: Logic symbols for NOR gates.
Truth Tables
i) Two Inputs
| Input | Output | |
|---|---|---|
| A | B | X |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
ii) Three Inputs
| Input | Output | ||
|---|---|---|---|
| A | B | C | X |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 |
iii) Four Inputs
| Input | Output | |||
|---|---|---|---|---|
| A | B | C | D | X |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 |
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